The present invention relates to semiconductor fabrication and more particularly to a method for fabricating a power semiconductor device such a power MOSFET.
Photolithography is a well known and prevalently used technique in the fabrication of semiconductor devices, such as power MOSFETs or the like. In general terms, photolithography involves the deposition of mask material over the surface of a semiconductor body and the selective removal of the mask material in order to form a mask having openings therein. The mask is then used to define features in the semiconductor body. For example, dopants can be implanted through the mask openings into the semiconductor body, or portions of the semiconductor body can be removed through the openings in order to recess or “trench” the semiconductor body as desired.
In a typical fabrication process, several masks may be required. For example, a mask may be required to define gate trenches, or a mask may be required to define source regions.
It is desirable to reduce the number of masks because generally speaking increasing the number of masks leads to more complexity in the fabrication process, which increases cost, and also more masks increase the chances of obtaining a higher percentage of defective parts, thereby reducing yield and increasing the overall cost.